The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a stack bank structure.
A semiconductor memory device in general includes an array of separate memory cells. The array of memory cells includes a plurality of rows and columns, the cross points of which are defined as memory cell addresses. The memory cells include a capacitor that stores charges as well as a transistor that serves to change or sense the charges of the capacitor. The charges are expressed as data bit; for example, a high voltage as the logic “1”, and a low voltage as the logic “0”. The data is stored in the memory during write operations and read from the memory during read operations.
In the conventional semiconductor memory devices, read operations connect the memory cells to the bit lines after activating the relevant word line(s). When the word lines are activated, the sense amplifier (also referred to as “the sense amp”) detects and amplifies data on activated bit lines. The semiconductor memory device selects the row and the column corresponding to the bit in order to access the memory cell. The sense amp determines whether “1” or “0” is stored in that memory position.
Meanwhile, a bank structure is adopted to reduce the capacitance load of the word line by reducing the length of the word line, thereby improving the access time and cycle time of the semiconductor memory device. That is, by disposing the memory cells of the semiconductor memory device in a bank unit, it is possible to form multiple bank structures that operate as the units of bank.
FIG. 1 is a schematic block structure of a semiconductor memory device with a conventional 4-bank structure.
Referring to FIG. 1, in the semiconductor memory device 100 of a 4-bank structure, one bank is divided into half-banks such that they are symmetrically aligned with the DQ pads DQ<0> to DQ<15>. One half-bank 110 includes of two core blocks 116, 118.
If one bank of the four banks, such as bank 0, is accessed, the half-bank 110 located above the DQ pads DQ<0>to DQ<15> sends/receives data to/from the DQ pads DQ<0> to DQ<7> through global input/output lines (GIO) 112, 114. The half-bank 120 under the DQ pads DQ<0> to DQ<15>sends/receives data to/from the DQ pads DQ<8> to DQ<15 through global input/output lines (GIO) 122, 124.
FIG. 2 is a block diagram showing the structure of a core block of the bank as illustrated in FIG. 1 supporting 4 bits prefetch. Referring to FIG. 2, the bank includes an even 0 block (EVEN0), an odd 0 block (ODD0), an even 1block (EVEN1) and an odd 1 block (ODD0).
The even 0 block (EVEN0), the odd 0 block (ODD0), the even 1 block (EVEN1), and the odd 1 block (ODD0) each includes a plurality of subblocks. The corresponding subblocks in each of the even 0 block (EVEN0), the odd 0block (ODD0), the even 1 block (EVEN1), and the odd 1 block (ODD0) form one mat. For example, the subblock 210 in the even 0 block (EVEN0), the subblock 220 of the odd 0 block (ODD0), the subblock 230 of the even 1 block (EVEN1) and the subblock 240 of the odd 1 block (ODD1) become a mat MAT<0>.
Each of the even 0 block (EVEN0), the odd 0 block (ODD0), the even 1 block (EVEN1), and the odd 1 block (ODD1) included in the core block is connected to four global input/output lines GIO through local input/output lines (LIO), a write driver (WDRV) (not shown), or input/output sense AMP (IOSA) 212, 222, 232, 242. Also, the even 0 block (EVEN0), the odd 0 block (ODD0), even 1block (EVEN1) and odd 1 block (ODD1) share the column select signal YI<0> to YI<n−1>.
In conventional bank structures supporting 4-bits prefetch, the DQ<0> pad sends/receives data to/from each of the memory blocks through the global input/output lines GIO_EV0<0>, GIO_EV1<0>, GIO_OD0<0>, and GIO_OD1<0>, and the DQ<1> pad sends/receives data to/from each memory block through the global input/output lines GIO_EV0<1>, GIO_EV1<1>, GIO_OD0<1>, and GIO_OD1<1>.
Further, the DQ<2> pad sends/receives data to/from each memory block through the global input/output lines GIO_EV0<2>, GIO_EV1<2>, IO_OD0<2>, and GIO_OD1<2>, and the DQ<3> pad sends/receives data to/from each memory block through the global input/output lines GIO_EV0<3>, GIO_EV1<3>, GIO_OD0<3>, and GIO_OD1<3>.
In the conventional bank structures supporting 4-bits prefetch, the write driver {WDRV} is enabled and the data on the global input/output line (GIO) is stored in the memory cell through the local input/output line LIO, a bit line sense amp (BLSA) unit 244 under the control of the subhole unit 246 in a case of writing the data. When reading the data stored in the memory cell, the data is delivered to the input/output sense amp 242 through the bit line sense amp unit 244, the local input/output line and the like under the control of the subhole unit 246, subsequently amplified and then recorded on the global input/output line.
FIG. 3 is a block structure diagram of the subhole unit (such as 246) and the bit line sense amp unit (such as 244) of FIG. 2, and FIG. 4 is a timing diagram for explaining operation of a semiconductor memory device with a conventional 4-bank structure. Referring to FIG. 3 and FIG. 4, active operations for banks 0 and 4 and read operations for banks 0 and 4 of the semiconductor memory device having the conventional 4-banks structure will be described now.
First, before the active operation proceeds, the bit line sense amp 340 equalizes the bit lines BL, /BL to a precharge level.
A mat control unit 310 outputs a bit line equalize signal BLEQ_M<n>_B<i> which is enabled “high” to the precharge unit 350. The precharge unit 350 turns on to allow the segment input/output lines SIO, /SIO to equalize to the precharge level of the bit line. Also, the mat control unit 310 outputs an input/output line connection signal BS_IO_M<n>_B<i> which is disabled “low” to an input/output connecting unit 370. The input/output connecting unit 370 is turned on to allow the segment input/output lines SIO, /SIO to disconnect from the local input/output lines LIO, /LIO.
A local input/output line reset signal generating unit 320 outputs a local input/output line reset signal LIO_RST_M<n>_B<i> which is enabled “high” to the reset unit 360. The reset unit 360 is turned on, thereby allowing the equalization of the local input/output lines LIO and /LIO to the precharge level of the local input/output line. Also, a column address decoder unit 330 outputs a column select signal YI<0:n−1>_B<i> that disables the bit line sense amp 340. The address signal outputted turns off the column select gate 342 of the bit line sense amp unit 340.
Next, the input of an active command ACT0 for the bank enables an internal active command signal RACT_B<0>. The bit line sense amp 340 of the mat selected by the row address GAX<0:xn> amplifies the data stored in the memory cell. At this time, the mat control unit 310 decreases the level of the bit line equalize signal BLEQ_M<0>_B<0> to “low” such that it stops equalizing the segment input/output lines SIO and /SIO. Also, the mat control unit 310 decreases the level of the input/output line connection signal BS_IO_M<0>_B<0> to “high” such that the segment input/output lines SIO and /SIO can connect to the local input/output lines LIO and /LIO respectively, thereby allowing the amplified data to move.
Next, input of the read command READ0 for the bank 0 from outside enables the internal column address select (CAS) command signal CAS_B<0>. The column address decoder unit 330 enables the column select signal YI<0>_B<0>corresponding to the column address GAY<0:yn> by synchronizing with the read/write strobe pulse RDWTSTBP.
Then, the bit line sense amp 340 delivers the amplified data on the bit lines BL and BL/ to the segment input/output lines SIO and /SIO. The data delivered to the segment input/output lines SIO and /SIO is inputted into the input/output sense amp (not shown) through the local input/output lines LIO and /LIO, amplified by the input/output sense amp and recorded on the global input/output line.
At this time, the mat control unit 310 outputs the local input/output line reset signal LIO_RST_M<0>_B<0>, of a “low” state, to the reset unit 360 while the column select signal YI<0>_B<0> is being enabled. The reset unit 360 is turned off to stop equalizing the local input/output lines LIO and /LIO. Therefore, the data of the segment lines SIO and /SIO can be moved in a stable manner to the local input/output lines LIO and /LIO. The active and read operations for bank 4 are the same as the active and read operations for bank 0.
Meanwhile, if the write command is inputted after the corresponding bank and row are activated, the corresponding write driver WDRV is enabled to cause the data on the global input/output lines to be recorded on each of the corresponding local input/output lines. The input/output connection signal of the mat selected when accessing the row is enabled to cause the data on the local input/output line to be delivered to the segment input/output line. The data on the segment input/output line is delivered to the bit line sense amp, which is enabled by the column select signal. The bit line sense amp amplifies the data delivered and stores it in the memory cell connected to the bit lines BL and /BL.
FIG. 5 is a schematic block structure diagram of the semiconductor memory device with an 8-bank stack structure 400 indicative of the prior art, which illustrates a semiconductor memory device with 16 DQ pads.
Referring to FIG. 5, in the semiconductor memory device with a conventional 8-bank stack structure, the eight banks are divided into half-banks, and two 4-banks are each located up and down with respect to the DQ pads DQ<0> to DQ<15>. One half-bank includes two core blocks. That is, one half-bank, e.g., down bank 410 includes of two core blocks 416, 418, and another half-bank, e.g., up bank 420 includes of two core blocks 426, 428.
If one of the eight banks is accessed, such as bank 0, the down bank 410 sends/receives the data to/from the DQ pads DQ<0> to DQ<7> through global input/output lines (GIO) 412, 414, and the up bank 420 stacked above the down bank 410 sends/receives the data to/from the DQ pads DQ<8> to DQ<15> through global input/output lines (GIO) 417, 419.
Such 8-bank stack structures are able to share the column select signal since the down bank 410 and the up bank 420 of bank 0 are stacked. However, since two half-banks 410, 420 are stacked up or down with respect to the DQ pads, the number of the global lines connecting each bank with the 16 DQ pads also increases. That is, the number of global input/output lines doubles compared to those of the bank structure of FIG. 1. Also, an up/down bank control logic (UP_DN CONTROL) is necessary to access all banks arranged in both directions with respect to the DQ pads.
The number of local input/output lines, write drivers and input/output sense amps that correspond to the global input/output lines also doubles. Referring to FIG. 6, it is apparent that as the number of global input/output lines increases in stacked banks, the number of local input/output lines, write drivers and input/output sense amps also increases.